A floating-gate FET is a basic semiconductor device in which a floating-gate electrode (often simply “floating gate”) overlies a channel region that extends between a pair of source/drain regions. A control-gate electrode (often simply “control gate”) overlies the floating gate. In some floating-gate FETs such as that described in U.S. Pat. No. 6,355,524 B1, a further electrode commonly referred to as the select-gate electrode (often simply “select gate”) is situated to the side of the floating and control gates above the channel region. This type of floating-gate FET is referred to here as a triple-gate split-gate device because it has three gate electrodes with the select gate split laterally apart from the floating gate.
A floating-gate FET has a threshold voltage, referred to here as the programmable threshold voltage, which can be adjusted subsequent to FET fabrication to control the FET's operational characteristics. During FET operation, one of the source/drain region functions as the source while the other functions as the drain. A control voltage is applied between the control gate and the source. With suitable potentials applied to other parts of the FET, including the select gate when the FET is a triple-gate split-gate device, the programmable threshold voltage is the value of the control voltage at which the FET switches between on and off conditions.
Floating-gate FETs are commonly employed as memory elements in EPROMs such as flash EPROMs. The storage of data in a floating-gate memory FET is controlled by variously placing charge carriers on, and removing charge carriers from, the floating gate to adjust the programmable threshold voltage. These two actions are generally referred to as “programming” and “erasure”. In a flash EPROM, all of the memory elements in a substantial portion of the EPROM are erased simultaneously.
Programming in a segment of a flash EPROM is performed after all the memory elements in that segment have been erased. In a flash EPROM whose memory elements consist of n-channel triple-gate floating-gate FETs, selected ones of the memory FETs in a selected row of the FETs are programmed by placing the sources and control gates of the selected FETs at suitable high programming voltages, holding their drains and channel regions at suitable low voltages, and applying suitable intermediate programming-enable voltages to their select gates. Electrons then travel from the drain of each selected FET to its source. Some of these electrons are drawn into the floating gate of each selected FET to raise its threshold voltage and place the FET in the programmed condition.
The drain of each remaining FET, i.e., each unselected FET, in the selected cell row is raised to a sufficiently high voltage that electrons do not travel from the drain of that FET to its source. This enables each unselected FET to remain in its prior condition, either erased or programmed if that FET was programmed in an earlier operation. Programming needs to be done carefully to avoid programming errors and unnecessary power consumption.